A semiconductor data storage device, such as a random access memory (“RAM”), static random access memory (“SRAM”), dynamic random access memory (“DRAM”), synchronous dynamic random access memory (“SDRAM”), magnetic random access memories (“MRAMs”), electronically erasable programmable read-only memory (EEPROM), and other forms of a memory, are designed to store data in a memory array of memory “cells”. Each memory cell, consisting of one or more transistors per bit of storage, is programmed during a write operation and is capable of maintaining the stored data, with or without memory refresh cycles, depending upon the type of memory. The memories may be included in any type of integrated circuit (“IC”), such as an IC that substantially contains only a memory array, as a dedicated memory IC, or included as an “embedded” memory as part of an IC containing additional, other circuits, such as embedded RAM, DRAM, SDRAM, etc., with a processor, digital signal processor, controller, wireless telecommunication IC or other communication IC.
A memory array is defined by a number of transistors, forming memory cells, generally arranged in a grid pattern having a plurality (or series) of rows and columns. Rows are typically utilized to select one or more data words, with the columns providing the input (for a memory write operation) and output (for a memory read operation) for each bit of each such word.
Memory arrays are tested in a wide variety of ways. External probe tests typically provide for continuity testing, and for testing of some AC and DC parameters. Many of these tests utilize one or more test patterns, in which test data is stored in the memory, read from the memory and then compared with the original test data. Typical patterns, for example, are all 1's, all 0's, checkerboard, stripe, marching, galloping, sliding diagonal, waling, and ping-pong, and test time varies with the selected pattern. Different patterns are also operative to detect different faults and failure modes during testing, such as “stuck at” faults, pattern sensitivity (such as interference and bit-line imbalance faults), multiple writing, refresh sensitivity, open and short circuits, leakage current faults, sense amplifier recovery, access time, voltage bump failures, decoder failures, and other faults and defects.
Self-testing, rather than external probe testing, has also been incorporated into many memory ICs, through the addition of additional test circuitry within the IC. Prior art built-in self-testing, however, typically determines whether there are no faults, thereby “passing ” the memory as acceptable, or determining that there is at least one fault, and thereby “failing” the memory as unacceptable. Such prior art self-testing does not differentiate between memory ICs which have a single memory defect, such as a defect affecting a single bit, and multiple memory defects (affecting at least two bits), such as a defect affecting a plurality of bits.
A representative, prior art memory self-testing circuit 10 is illustrated in FIG. 1. Input test data is compared, bit position by bit position (i.e., by corresponding column), with the stored test data from the memory 20 under test, in comparator 50. In the event that the stored data does not match the test data at a given bit position, an output indicating such a failure (such as a logic 1 or high voltage state) is provided on one of the corresponding comparator output lines 55. Prior art memory self-testing circuits (such as 10) are incapable of differentiating multiple bit errors from a single bit error (such as one error versus multiple errors) because, following comparison of test data with stored data, any indicator of failure for a bit position is typically “OR'd” (OR gate 60) with the indicators of all other bit positions. If any one bit position has a failure, the output of the OR gate 60 will indicate a failure. The outcome from the OR gate 60 is then latched (with feedback) (latch 65), so that once a failure has occurred, it will not be overwritten, and the failure indicator 70 will indicate a memory failure. As a consequence of the OR process, the self-testing circuit provides information that at least one error has occurred, but cannot determine that more than one error may have occurred.
Other types of memory testing are also utilized in the prior art, such as testing which may be used with memory ICs having redundant or “spare” portions of the memory array. In such testing, memory ICs having no errors may be fully passed, and memory ICs having one or more bit errors may be “conditionally passed”, in a first tier of testing. Those memory ICs which have been conditionally passed may then be physically repaired by disabling one or more rows or columns having defects, and substituting new rows or columns from the additional, redundant hardware available in the memory IC, potentially followed by additional testing. This testing requires tracking of any defect of every cell of the array. Moreover, the ability to utilize or repair such conditionally passed ICs is not assured by a definitive count or other test control criteria. More particularly, memory ICs having up to a predetermined level of bit errors cannot be fully and automatically passed, as those memories may or may not be repairable in fact. In addition, such testing requires the availability of spare or redundant parts of a memory IC, increasing memory size requirements without increasing the actual available memory. Such testing may also require several levels of testing, the initial conditional testing, followed by repair and potentially additional testing.
These current self-testing modes also do not utilize and take advantage of error correcting capabilities which may be available in the coding process for the data to be stored in the memory. Such error correcting capabilities are typically utilized to correct for “soft” errors, such as memory read errors which may occur due to external interference, such as from cosmic rays, other forms of background radiation, or other noise sources. As a consequence, by only detecting that there is at least one bit error, prior art memory self-testing fails memory ICs having a single defect, even though the single bit error could be corrected through error correction codes. By not differentiating between levels or amounts of potential defects, the prior art memory self-testing results in discarding memory ICs which are, in fact, capable of being utilized within IC error specifications. Such prior art memory self-testing, therefore, decreases the available IC yield from IC manufacturing.
As a consequence, a need remains to provide a built-in self-testing circuit for a memory array which can differentiate between levels or amounts of potential defects. Such a built in memory self-testing circuit should provide for detecting bit errors, and for differentiating memory ICs having bit errors which are correctable within the capability of a selected error correction code from memory ICs having bit errors which are not correctable or which otherwise exceed the capability of the selected error correction code. Such a built in memory self-testing circuit should not require additional, redundant memory, should not require defect tracking by specific memory cell, and should provide a definitive rather than conditional test result.